In the integrated circuit (IC) industry, copper interconnects are typically utilized to connect one electrical point to another electrical point along the surface of a semiconductor wafer. In order to form these copper interconnects, a copper electroplating or electroless process is typically utilized to form a blanket copper layer over the wafer. This blanket copper layer is then chemically-mechanically polished to form the copper interconnects within trenches previously etched in dielectric material. However, conventional blanket copper electroplating or electroless plating causes some adhesion problems at the periphery of the semiconductor wafer which increases particulate problems and reduces yield.
As an example, FIG. 1 illustrates the prior art copper electroplating operation. In FIG. 1, a base layer 11 or substrate 11 is provided. The base layer 11 contains the semiconductor wafer along with any dielectric and conductive layers needed over the semiconductor wafer to form active electrical devices. In order to connect these electrical devices to each other over the wafer surface, a barrier layer 13 is first formed over the substrate 11. The barrier layer 13 prevents subsequently-formed copper regions from adversely affecting underlying semiconductor and metallic regions. Overlying the barrier layer 13 is formed a seed layer 15. It has been found in the art that the seed layer 15 should be separated from the edge of the substrate 11 by an edge exclusion distance 20 as illustrated in FIG. 1. The edge exclusion region 20 is utilized for the electroplating operation to avoid some wafer edge-effect problems, but the edge exclusion also creates some material interface problems as discussed below.
If seed layer 15 were to extend to the very edge of the wafer 11, then the copper electroplating operation would result in copper material forming beyond the edge of the wafer and potentially down a sidewall and backside of the wafer. This additional sidewall and backside material cannot be removed by conventional chemical etching or chemical mechanical polishing. This peripheral copper formation would thereby create sidewall abnormalities that could result in damage to the wafer or the inability of the wafer to be properly processed within semiconductor equipment. Therefore, the seed layer 15 is separated from the edge of the wafer 11 via the exclusion region 20 to avoid these problems, but this exclusion region creates yet another problem discussed below.
After formation of the seed layer, the seed layer 15 is exposed to a liquid electroplating bath whereby a copper layer 17 is electroplated not only from the seed layer 15 but from exposed portions of the barrier layer 13 in the edge exclusion region 20 as illustrated in FIG. 1. The seed layer 15 will electroplate copper more effectively than the barrier layer 13 thereby resulting in the edge exclusion copper topography illustrated in FIG. 1 for the copper layer 17. Note that due to the exclusion region, copper region 17 is now in direct contact with a barrier region 13.
As illustrated in FIG. 2, adhesion between a copper layer 17 and a typical barrier layer 13, such as titanium nitride (TiN), is extremely poor. Therefore, when copper 17 is in contact with the barrier 13 in the exclusion region 20, as illustrated in FIG. 2, flaking or peeling 19 between the copper 17 and the barrier 13 is inevitable. This flaking, delamination, or peeling 19 between the copper 17 and the barrier layer 13 in the edge exclusion region 20 reduces the yield of semiconductor devices and creates particulate problems in processing chambers. Device yield along the periphery of the wafer is impacted most profoundly.
This problem has been solved or reduced in severity by placing an intermediate layer between the layer 13 and the seed 15. However, this additional intermediate layer, while preventing the peeling shown in FIG. 2, is usually more resistive that desired and will increase the resistivity of the inlaid interconnects and contacts formed over the IC. This increase in resistivity is clearly disadvantageous even though the peeling problem of FIG. 2 is reduced or avoided.
Therefore, a need exists for a copper electroplating process which prevents electroplating of copper on an exposed edge exclusion region of a semiconductor wafer whereby barrier material is not placed in contact with electroplated copper.